US 12,488,838 B2
Memory device including page buffer circuit
Yongsung Cho, Suwon-si (KR); Inho Kang, Suwon-si (KR); Insu Kim, Suwon-si (KR); and Jaehue Shin, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 15, 2023, as Appl. No. 18/197,258.
Claims priority of application No. 10-2022-0100677 (KR), filed on Aug. 11, 2022.
Prior Publication US 2024/0055055 A1, Feb. 15, 2024
Int. Cl. G11C 7/00 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2023.01)
CPC G11C 16/24 (2013.01) [G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of memory cells; and
a page buffer circuit comprising a plurality of page buffer units respectively connected to the plurality of memory cells via a plurality of bit lines, and a plurality of cache latches respectively corresponding to the plurality of page buffer units,
wherein each of the plurality of page buffer units comprises a pass transistor that is connected to a corresponding sensing node and is driven according to a pass control signal, and
wherein the memory device is configured such that in a data sensing period, a sensing node of a selected page buffer unit among the plurality of page buffer units is actively connected to a sensing node of an unselected page buffer unit among the plurality of page buffer units.