US 12,488,835 B2
Wordline boost by charge sharing in a memory device
Mattia Robustelli, Milan (IT); and Innocenzo Tortorelli, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 24, 2022, as Appl. No. 17/752,785.
Prior Publication US 2023/0386572 A1, Nov. 30, 2023
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0028 (2013.01) [G11C 13/0004 (2013.01); G11C 13/003 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory array having at least one first tile and at least one second tile, each of the first and second tiles including memory cells;
access lines configured to select at least a portion of the memory cells in the first and second tiles; and
at least one controller configured to program the selected memory cells, wherein:
the selected portion of the memory cells in the first tile are programmed by applying a first voltage to a first access line of the access lines;
the selected portion of the memory cells in the second tile are programmed by applying a second voltage to a second access line of the access lines;
the first and second voltages are applied in a counter-phase manner; and
the second voltage is boosted by charge sharing between the first and second access lines;
wherein applying the first and second voltages in a counter-phase manner comprises applying the first and second voltages in parallel using opposite polarities.