US 12,488,833 B2
Variable read method for read time performance improvement of non-volatile memory
Albert Chen, Milpitas, CA (US); Jiahui Yuan, Fremont, CA (US); Sarath Puthenthermadam, San Jose, CA (US); and Akira Okada, Yokohama (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on Jul. 24, 2023, as Appl. No. 18/225,344.
Claims priority of provisional application 63/446,098, filed on Feb. 16, 2023.
Prior Publication US 2024/0282363 A1, Aug. 22, 2024
Int. Cl. G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the memory holes and configured to:
read the memory cells in a read operation, and
adjust, based on an amount of cycling of the memory cells, at least one word line read pre-charge time in which unselected ones of the plurality of word lines are pre-charged and ramp up to a target level and selected ones of the plurality of word lines ramp up to a spike voltage at the target level and back down to a steady state voltage.