US 12,488,832 B2
Embedded dynamic random-access memory (eDRAM) to operate based on data access characteristics
Abhishek Anil Sharma, Portland, OR (US); Pushkar Ranade, San Jose, CA (US); Wilfred Gomes, Portland, OR (US); and Rajabali Koduri, Saratoga, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,286.
Prior Publication US 2023/0317145 A1, Oct. 5, 2023
Int. Cl. G11C 11/401 (2006.01); G06F 12/0846 (2016.01); G06F 12/0897 (2016.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/4096 (2013.01) [G06F 12/0848 (2013.01); G06F 12/0897 (2013.01); G11C 11/4094 (2013.01); G11C 11/419 (2013.01); G06F 2212/604 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first array comprising a first plurality of memory cells;
a second array comprising a second plurality of memory cells, both first and second arrays to store data of a processor, the second plurality of memory cells implementing a selector transistor of a memory cell within using a thin-film transistor (TFT); and
a memory control circuit to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits, wherein an access frequency of each of the first and second sets of bits is determined based on a frequent value caching indication of the first and second sets of bits.