| CPC G11C 11/40615 (2013.01) [G11C 11/4072 (2013.01); G11C 11/4076 (2013.01); H03K 23/002 (2013.01)] | 19 Claims |
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1. A counting control circuit, comprising a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit connected to a clock terminal of the counting statistic circuit,
wherein the logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal, and
the counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal, wherein the first identification signal indicates a generation of a command signal for performing a first operation, and the first identification signal is in a valid state under a condition that a counting value meets a preset condition;
wherein the logic control circuit comprises:
a first driving circuit, configured to perform driving on the first clock signal, to obtain a first intermediate signal; and
a first logic circuit, configured to perform a logical operation on the first intermediate signal and the first identification signal, to obtain the counting clock signal;
wherein the first logic circuit comprises:
a first delay inverting circuit, configured to delay and invert the first identification signal, to obtain a second intermediate signal;
a first NAND gate, configured to perform a NAND logical operation on the first intermediate signal and the second intermediate signal, to obtain a third intermediate signal; and
a second NOT gate, configured to perform a NOT logical operation on the third intermediate signal, to obtain the counting clock signal.
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