US 12,488,814 B2
DRAM interface mode with improved channel integrity and efficiency at high signaling rates
Frederick A. Ware, Los Altos Hills, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 8, 2024, as Appl. No. 18/629,086.
Application 18/629,086 is a continuation of application No. 17/954,086, filed on Sep. 27, 2022, granted, now 11,955,200.
Application 17/954,086 is a continuation of application No. 17/299,554, granted, now 11,468,925, issued on Oct. 11, 2022, previously published as PCT/US2019/064052, filed on Dec. 2, 2019.
Claims priority of provisional application 62/774,591, filed on Dec. 3, 2018.
Prior Publication US 2024/0339137 A1, Oct. 10, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 8/18 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1066 (2013.01); G11C 7/1069 (2013.01); G11C 7/1093 (2013.01); G11C 7/1096 (2013.01); G11C 8/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) memory device, comprising:
a first command/address (C/A) interface to receive from a memory controller a first read command and a second read command directed to a first bank group of memory for first read data and second read data;
a second command/address (C/A) interface to receive from the memory controller a third read command and a fourth read command directed to a second bank group of memory for third read data and fourth read data;
transmit circuitry to transmit the first read data and the second read data via a first data link interface and to transmit the third read data and the fourth read data via a second data link interface;
wherein for a first operating mode, the first read data and the second read data are transmitted for receipt by the memory controller after respective first delays following transmission of the first read command and the second read command by the memory controller; and
wherein for a second operating mode, the first read data and the second read data are transmitted for receipt by the memory controller after a second delay and a third delay, respectively, following transmission of the first read command and the second read command by the memory controller, the second delay and the third delay being different from the respective first delays and from each other.