| CPC G09G 5/395 (2013.01) [G09G 5/06 (2013.01)] | 9 Claims |
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1. A device for controlling a data interface of a display apparatus, the device comprising:
a timing controller configured to encode one data transfer packet including image data of a plurality of colors according to a pixel clock to output the one data transfer packet to an interface line; and
a source driver configured to receive the one data transfer packet through the interface line and decode the one data transfer packet according to the pixel clock to recover the image data of the plurality of colors,
wherein the image data of the plurality of colors includes first image data of a first color and second image data of a second color arranged between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value different than the first logic value,
wherein a most significant bit of the first image data is arranged closer to the first delimiter signal than a least significant bit of the first image data,
wherein a most significant bit of the second image data is arranged closer to the second delimiter signal than a least significant bit of the second image data,
wherein the timing controller is further configured to arrange first indication data and second indication data between the first delimiter signal and the first image data within the one data transfer packet, and
wherein, when the first indication data has the first logic value, upper bits of the first image data all have the first logic value, and when the second indication data has the first logic value, upper bits of the second image data all have the second logic value.
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