US 12,488,767 B2
Display apparatus and electronic device
Susumu Kawashima, Atsugi (JP); Koji Kusunoki, Isehara (JP); Kazunori Watanabe, Machida (JP); and Naoto Kusumoto, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 5, 2023, as Appl. No. 18/529,032.
Application 18/529,032 is a continuation of application No. 17/844,931, filed on Jun. 21, 2022, granted, now 11,842,705.
Application 17/844,931 is a continuation of application No. 17/298,999, granted, now 11,373,610, issued on Jun. 28, 2022, previously published as PCT/IB2019/060823, filed on Dec. 16, 2019.
Claims priority of application No. 2018-242749 (JP), filed on Dec. 26, 2018.
Prior Publication US 2024/0105138 A1, Mar. 28, 2024
Int. Cl. G09G 3/36 (2006.01); G02F 1/1368 (2006.01); H10K 59/131 (2023.01)
CPC G09G 3/3688 (2013.01) [G02F 1/1368 (2013.01); G09G 3/3648 (2013.01); G09G 3/3696 (2013.01); G09G 2300/0426 (2013.01); G09G 2330/021 (2013.01); H10K 59/131 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A display apparatus comprising:
a pixel comprising a first transistor, a second transistor, a third transistor, a capacitor, and a circuit which comprises a display device,
wherein a first electrode of the capacitor is electrically connected to one of a source and a drain of the first transistor and the circuit,
wherein a second electrode of the capacitor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring,
wherein, in a first period, the first transistor and the third transistor are each in a conduction state, the second transistor is a non-conduction state, a first data is supplied to the first electrode of the capacitor through the first transistor, and a second data is supplied to the second electrode of the capacitor through the third transistor, and
wherein, in a second period, the first transistor and the third transistor are each in a non-conduction state, the second transistor is a conduction state, and the first data is supplied to the first electrode of the capacitor through the second transistor.