US 12,488,766 B2
Gate driver
Minjoo Kim, Yongin-si (KR); Minwoo Byun, Yongin-si (KR); Kyonghwan Oh, Yongin-si (KR); Yang-Hwa Choi, Yongin-si (KR); and Donghwan Jeon, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on May 28, 2024, as Appl. No. 18/675,139.
Claims priority of application No. 10-2023-0129251 (KR), filed on Sep. 26, 2023; and application No. 10-2023-0143280 (KR), filed on Oct. 24, 2023.
Prior Publication US 2025/0104596 A1, Mar. 27, 2025
Int. Cl. G09G 3/36 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H03K 3/012 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); H03K 3/012 (2013.01); G09G 2310/0267 (2013.01); G09G 2330/021 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A gate driver comprising a plurality of stages, wherein at least one of the stages includes:
a control circuit configured to control a first control node in response to a first carry clock signal;
a node separation transistor connected between the first control node and a second control node;
a carry output circuit configured to output a carry signal in response to a voltage of the second control node; and
a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.