US 12,488,759 B2
Shift register unit, drive control circuit, display apparatus and driving method
Benlian Wang, Beijing (CN); Yue Long, Beijing (CN); and Hai Zheng, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/688,163
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 29, 2022, PCT No. PCT/CN2022/134975
§ 371(c)(1), (2) Date Feb. 29, 2024,
PCT Pub. No. WO2024/113153, PCT Pub. Date Jun. 6, 2024.
Prior Publication US 2025/0124880 A1, Apr. 17, 2025
Int. Cl. G09G 3/3266 (2016.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3677 (2013.01); G11C 19/287 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0247 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
an input circuit configured to, in response to a signal from a first clock signal terminal, provide a signal from the input signal terminal to a first node;
a control circuit configured to control a signal at a second node;
a first output circuit configured to, in response to a signal from the first node, provide a signal from a first reference voltage signal terminal to an output signal terminal;
a second output circuit configured to, in response to a signal from the second node, provide a signal from a second reference voltage signal terminal to the output signal terminal; and
a noise reduction circuit configured to, in response to a signal from a noise reduction signal terminal, provide a signal from a third reference voltage signal terminal to the second node to control the second output circuit to stop outputting a signal;
wherein the first node comprises a first sub-node and a second sub-node; and
the shift register unit further comprises a conduction circuit; wherein
the first sub-node is coupled to the second sub-node via the conduction circuit, and the conduction circuit is configured to, in response to a signal from a fourth reference voltage signal terminal, conduct the first sub-node with the second sub-node;
the input circuit is further configured to, in response to the signal from the first clock signal terminal, provide the signal from the input signal terminal to the first sub-node; and
the first output circuit is further configured to, in response to a signal at the second sub-node, provide the signal from the first reference voltage signal terminal to the output signal terminal.