US 12,488,749 B2
Display substrate and display apparatus
Longfei Fan, Beijing (CN); Yaoxi Ma, Beijing (CN); Dachao Li, Beijing (CN); Shanghong Jiang, Beijing (CN); Pengcheng Lu, Beijing (CN); Shengji Yang, Beijing (CN); and Xiaochuan Chen, Beijing (CN)
Assigned to Yunnan Invensight Optoelectronics Technology Co., Ltd., Yunnan (CN); and Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 18/558,265
Filed by Yunnan Invensight Optoelectronics Technology Co., Ltd., Yunnan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Dec. 19, 2022, PCT No. PCT/CN2022/140139
§ 371(c)(1), (2) Date Oct. 31, 2023,
PCT Pub. No. WO2024/130510, PCT Pub. Date Jun. 27, 2024.
Prior Publication US 2025/0087152 A1, Mar. 13, 2025
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0465 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/061 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
an array layer, the array layer including a silicon substrate, a plurality of pixels and a plurality of pixel driving circuits corresponding to the plurality of pixels; wherein
a pixel driving circuit of the plurality of pixel driving circuits includes a driving sub-circuit, a storage sub-circuit and a reset sub-circuit; wherein
the storage sub-circuit includes a first capacitor and a second capacitor connected in series; a first plate of the first capacitor is coupled to a first node, and a second plate of the first capacitor is coupled to a second node; a third plate of the second capacitor is coupled to the second node, and a fourth plate of the second capacitor is coupled to a first voltage signal terminal;
the driving sub-circuit is coupled to the first node, the second node and a third node, and the driving sub-circuit is configured to generate a driving current under control of the storage sub-circuit and transmit the driving current to a light-emitting device; and
the reset sub-circuit is coupled to a third scan signal terminal, a second voltage signal terminal and the third node; the reset sub-circuit is configured to transmit a second voltage signal at the second voltage signal terminal to the third node under control of a third scan signal from the third scan signal terminal in a light-emitting period; and the reset sub-circuit includes a third transistor, a gate of the third transistor is coupled to the third scan signal terminal, a first electrode of the third transistor is coupled to the second voltage signal terminal, and a second electrode of the third transistor is coupled to the third node;
wherein in a direction perpendicular to the array layer, the first plate, the second plate, the third plate and the fourth plate have an overlapping region therebetween;
wherein the driving sub-circuit includes a driving transistor, the pixel driving circuit further includes a first transistor and a second transistor,
the first transistor, the second transistor and the driving transistor are P-type transistors; the first transistor, the second transistor and the driving transistor are all located in an N-well region of the silicon substrate; and
the third transistor is an N-type transistor; the third transistor is located in a deep N-well region of the silicon substrate.