| CPC G09G 3/3233 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01)] | 18 Claims |
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1. A pixel of a display device, the pixel comprising:
a first capacitor coupled between a first power supply voltage line and a first node;
a first transistor including a gate coupled to the first node, a first terminal coupled to a second node, and a second terminal coupled to a third node;
a second transistor including a gate configured to receive a writing signal, a first terminal coupled to a data line, and a second terminal coupled to the second node;
a third transistor including a gate configured to receive a compensation signal, a first terminal coupled to the third node, and a second terminal coupled to a fourth node;
a fourth transistor including a gate configured to receive an initialization signal, a first terminal coupled to the fourth node, and a second terminal coupled to an initialization voltage line;
a fifth transistor including a gate configured to receive a first emission signal, a first terminal coupled to the first power supply voltage line, and a second terminal coupled to the second node;
a light emitting element including an anode coupled to the third node, and a cathode coupled to a second power supply voltage line;
a seventh transistor including a gate configured to receive a bypass signal, a first terminal coupled to an anode initialization voltage line, and a second terminal coupled to the anode of the light emitting element, wherein the bypass signal is a previous writing signal for a previous pixel row that is physically immediately adjacent to a pixel row of the pixel; and
an eighth transistor including a gate configured to receive a second emission signal having a phase different from a phase of the first emission signal, a first terminal coupled to the first node, and a second terminal coupled to the fourth node.
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