| CPC G09G 3/2092 (2013.01) [G09G 3/3674 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] | 8 Claims |
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1. A gate driving device, comprising:
a plurality of gate driving circuits, configured to generate a plurality of gate driving signals having different timing and change a series connection mode between the plurality of gate driving circuits in response to a scan selection signal, wherein the series connection mode corresponds to a gate driving scanning mode of the gate driving device; and
a control circuit, coupled to a plurality of candidate gate driving circuits among the plurality of gate driving circuits, configured to select one of the plurality of candidate gate driving circuits as an initial stage gate driving circuit per one scanning cycle,
wherein the scan selection signal having different digital values corresponds to different one among a plurality of interlace scanning modes,
wherein in the plurality of interlace scanning modes, a plurality of gate driving circuits that are not adjacent to each other among the gate driving circuits generate a plurality of gate driving signals having a pulse sequentially,
wherein the scan selection signal having a first digital value corresponds to a first interlace scanning mode among a plurality of interlace scanning modes, wherein the scan selection signal having a second digital value corresponds to a second interlace scanning mode among the plurality of interlace scanning modes,
wherein a “n”th stage gate driving circuit among the plurality of gate driving circuits comprises:
a gate driving unit, configured to receive an input gate driving signal from one of other gate driving circuits and generate an output gate driving signal according to the input gate driving signal, wherein a timing of the output gate driving signal lags behind a timing of the input gate driving signal; and
a path selecting circuit, comprises:
a first switch, wherein a first terminal of the first switch is connected to the output terminal of the “n”th stage gate driving circuit and a second terminal of the first switch is connected to an input terminal of a “n+a” th stage gate driving circuit, and wherein the first switch is turned-on in response to the scan selection signal having the first digital value, wherein in the first interlace scanning mode, the first switch is turned on and transmits the output gate driving signal to the “n+a” th stage gate driving circuit; and
a second switch, wherein a first terminal of the second switch is connected to the output terminal of the “n”th stage gate driving circuit and a second terminal of the second switch is connected to an input terminal of a “n+b” th stage gate driving circuit, and wherein the second switch is turned-on in response to the scan selection signal having the second digital value different from the first digital value, wherein in the second interlace scanning mode, the second switch is turned on and transmits the output gate driving signal to the “n+b” th stage gate driving circuit,
wherein the “a” and “b” are positive integers, and
wherein when the series connection mode corresponds to the interlace scanning modes of the gate driving device, the control circuit changes the selected one of the plurality of candidate gate driving circuits as the initial stage gate driving circuit per one scanning cycle of a plurality of scanning cycles indicated by pulses of an initial signal, and
wherein the candidate gate driving circuits respectively operates in the plurality of scanning cycles, and the candidate gate driving circuits generating the gate driving signals in one of the plurality of scanning cycles are different from the candidate gate driving circuits generating the gate driving signals in another of the plurality of scanning cycles.
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