| CPC G09G 3/2074 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/027 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/046 (2013.01)] | 11 Claims |

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1. A display panel, comprising:
a plurality of first sub-pixels;
a plurality of second sub-pixels;
a first source driver chip, comprising a first delay module having a first delay interval and/or a first delay level, wherein the first delay module is electrically connected to the plurality of first sub-pixels and comprises a first delay load; and
a second source driver chip, comprising a second delay module having a second delay interval and/or a second delay level, wherein the second delay module is electrically connected to the plurality of second sub-pixels and comprises a second delay load,
wherein the second source driver chip further comprises a first compensation module electrically connected to the plurality of second sub-pixels and the second delay module, and the first compensation module is configured to compensate for a difference in equivalent resistance between the second delay load and the first delay load according to a difference between the second delay interval and the first delay interval, and/or according to a difference between the second delay level and the first delay level.
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