US 12,488,722 B2
Pixel drive circuit and timing control method therefor, and display panel
Maoxia Zhu, Guangdong (CN)
Assigned to Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong (CN)
Filed by Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd., Guangdong (CN)
Filed on Dec. 18, 2023, as Appl. No. 18/542,941.
Claims priority of application No. 202310958271.7 (CN), filed on Jul. 31, 2023.
Prior Publication US 2025/0046227 A1, Feb. 6, 2025
Int. Cl. G09G 3/20 (2006.01); G09G 3/32 (2016.01)
CPC G09G 3/2014 (2013.01) [G09G 3/2025 (2013.01); G09G 3/32 (2013.01); G09G 2300/043 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/045 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A pixel drive circuit, comprising:
a drive module;
a pulse modulation module configured to be enabled and disenabled based on a first scanning signal and a second scanning signal, to convert a data drive signal into a modulation signal of a drive current, and provide the modulation signal to the drive module, wherein the modulation signal is a pulse width modulation signal or a pulse amplitude modulation signal; and
a light-emitting device,
wherein the drive module is connected to the pulse modulation module and the light-emitting device, to control on-off of the drive current based on the modulation signal to control the light-emitting device to emit light;
the pulse modulation module comprises a dual-gate transistor;
the dual-gate transistor comprises a first gate, a second gate, a first electrode, and a second electrode; and
the first gate receives the first scanning signal, the second gate receives the second scanning signal, the first electrode receives the data drive signal, and the second electrode is connected to the drive module;
wherein the drive module comprises:
a drive transistor, wherein the drive transistor comprises a gate, a first end, and a second end; and
wherein the gate of the drive transistor is connected to the second electrode, the first end receives a voltage signal, and the second end is connected to the light-emitting device;
wherein the pixel drive circuit further comprises a storage capacitor, wherein two ends of the storage capacitor are electrically connected to the gate and the second end of the drive transistor respectively;
wherein a drive cycle of the pixel drive circuit comprises N sub-periods, wherein N is a natural number greater than or equal to 2;
wherein the pulse modulation module is configured to, in each sub-period of preceding N−1 sub-periods, perform data pulse width modulation, convert the data drive signal into the pulse width modulation signal, and provide the pulse width modulation signal to the drive module; the pulse modulation module is configured to, in an Nth sub-period, perform data pulse amplitude modulation, convert the data drive signal into the pulse amplitude modulation signal, and provide the pulse amplitude modulation signal to the drive module.