| CPC G09G 3/20 (2013.01) [H10D 86/441 (2025.01); H10D 86/60 (2025.01); G09G 2300/0408 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01)] | 12 Claims |
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1. A display panel, comprising:
a display part comprising a plurality of sub-pixel rows, wherein each of the sub-pixel rows comprises a plurality of sub-pixel units each provided with a pixel circuit; and
a drive part, wherein the drive part and the display part are arranged in a first direction, the drive part comprises a first drive circuit and a second drive circuit that are arranged in the first direction, the second drive circuit is disposed between the first drive circuit and the display part, the first drive circuit comprises a plurality of first drive modules arranged in a second direction, and the second drive circuit comprises a plurality of second drive modules arranged in the second direction,
wherein each of the first drive modules is electrically connected to the pixel circuit in each of the sub-pixel units of each of k ones of the sub-pixel rows adjacent to the each of the first drive modules, and each of the second drive modules is electrically connected to the pixel circuit in each of the sub-pixel units of each of j ones of the sub-pixel rows adjacent to the each of the second drive modules, where each of k and j is a positive integer, k is less than or equal to j, and j is greater than or equal to 2,
wherein the pixel circuit comprises a switch transistor, a drive transistor, and a first reset transistor, the switch transistor and the drive transistor are connected to a first reset node, and the first reset transistor and the drive transistor are connected to a second reset node,
wherein the first drive modules are cascaded, and each of the first drive modules has a first signal output terminal,
wherein the second drive modules are cascaded, and each of the second drive modules has a second signal output terminal, and
wherein, in a case that k is equal to 1 and j is equal to 2, the first signal output terminal of a n-th stage one of the first drive modules is connected to a gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a n-th one of the sub-pixel rows, the first signal output terminal of a (n+1)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+1)-th one of the sub-pixel rows, and the second signal output terminal of an a-th stage one of the second drive modules is connected to a gate of the first reset transistor of the pixel circuit in each of the sub-pixel units of each of the n-th one and the (n+1)-th one of the sub-pixel rows, where n is a positive integer, and a is a positive integer equal to (n+1)/2; or
in a case that k is equal to 1 and j is equal to 4, the first signal output terminal of a n-th stage one of the first drive modules is connected to a gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a n-th one of the sub-pixel rows, the first signal output terminal of a (n+1)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+1)-th one of the sub-pixel rows, the first signal output terminal of a (n+2)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+2)-th one of the sub-pixel rows, the first signal output terminal of a (n+3)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+3)-th one of the sub-pixel rows, and the second signal output terminal of an a-th stage one of the second drive modules is connected to a gate of the first reset transistor of the pixel circuit in each of the sub-pixel units of each of the n-th one to the (n+3)-th one of the sub-pixel rows, where n is a positive integer, and a is a positive integer equal to (n+3)/4; or
wherein the each of the first drive modules has a third signal output terminal, and in a case that k is equal to 2 and j is equal to 2, the first signal output terminal of a b-th stage one of the first drive modules is connected to a gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a n-th one of the sub-pixel rows, the third signal output terminal of the b-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+1)-th one of the sub-pixel rows, and the second signal output terminal of an a-th stage one of the second drive modules is connected to a gate of the first reset transistor of the pixel circuit in each of the sub-pixel units of each of the n-th one and the (n+1)-th one of the sub-pixel rows, where n is a positive integer, and each of a and b is a positive integer equal to (n+1)/2; or
wherein the each of the first drive modules has a third signal output terminal, and in a case that k is equal to 2 and j is equal to 4, the first signal output terminal of a b-th stage one of the first drive modules is connected to a gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a n-th one of the sub-pixel rows, the third signal output terminal of the b-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+1)-th one of the sub-pixel rows, the first signal output terminal of a (b+1)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+2)-th one of the sub-pixel rows, the third signal output terminal of the (b+1)-th stage one of the first drive modules is connected to the gate of the switch transistor of the pixel circuit in each of the sub-pixel units of a (n+3)-th one of the sub-pixel rows, and the second signal output terminal of an a-th stage one of the second drive modules is connected to a gate of the first reset transistor of the pixel circuit in each of the sub-pixel units of each of the n-th one to the (n+3)-th one of the sub-pixel rows, where n is a positive integer, b is a positive integer equal to (n+1)/2, and a is a positive integer equal to (n+3)/4.
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