US 12,488,218 B2
Lossless tiling in convolution networks—padding and re-tilling at section boundaries
Tejas Nagendra Babu Nama, Sunnyvale, CA (US); Ruddhi Chaphekar, Santa Clara, CA (US); Ram Sivaramakrishnan, San Jose, CA (US); Raghu Prabhakar, San Jose, CA (US); Sumti Jairath, Santa Clara, CA (US); Junjue Wang, San Mateo, CA (US); Kaizhao Liang, Palo Alto, CA (US); Adi Fuchs, West Windsor, NJ (US); Matheen Musaddiq, Austin, TX (US); and Arvind Krishna Sujeeth, San Francisco, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Jun. 30, 2021, as Appl. No. 17/364,141.
Application 17/364,141 is a division of application No. 17/216,652, filed on Mar. 29, 2021, granted, now 11,227,207.
Prior Publication US 2022/0309318 A1, Sep. 29, 2022
Int. Cl. G06N 3/04 (2023.01)
CPC G06N 3/04 (2013.01) 20 Claims
OG exemplary drawing
 
1. A non-transitory computer readable storage medium impressed with computer program instructions that, when executed on a processor, implement a method comprising:
generating by an output processing node of a first section of a processing graph, a plurality of output tiles of an output tensor, individual output tiles in the plurality of output tiles having a first size;
writing the plurality of output tiles of the output tensor in a memory, wherein the writing comprises zero-padding the plurality of output tiles of the output tensor in the memory to create a zero-padded plurality of output tiles;
tiling the zero-padded plurality of output tiles of the output tensor to generate a plurality of input tiles of an input tensor, individual input files in the plurality of input tiles having a second size that is larger than the first size; and
processing the plurality of input tiles of the input tensor in a second section of the processing graph.