| CPC G06F 15/7825 (2013.01) | 23 Claims |
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1. An on-chip network, comprising:
a two-dimensional array of network nodes fabricated in a die, wherein each one of the network nodes comprises:
a plurality of input ports; and
a plurality of output ports,
each input port of the respective network node configured to:
receive an asynchronous input signal comprising a packet that includes data and a destination address,
receive a request valid input signal,
while the request valid input signal is asserted, route the data to a respective one output port of the plurality of output ports of the respective network node according to the destination address,
asynchronously assert a route request signal input to the respective one output port for transmitting the packet, and
in response to determining that the packet is accepted, assert an acknowledge output signal; and
each output port configured to:
receive route request input signals from at least two input ports of the plurality of input ports of the respective network node,
select the packet provided by one of the at least two input ports for which the route request signal input is asserted as a selected packet,
asynchronously output an output signal comprising the selected packet;
assert an output request valid signal, and
in response to assertion of an acknowledge input, negate the output request valid signal and assert a route acknowledge output signal to the one of the at least two input ports indicating acceptance of the packet for transmission.
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