US 12,487,961 B2
Scalable and modular bus controller including page memory PLD architecture
Rajesh Madathikandam, Karnataka (IN); Robin David Hill, Solihull (GB); Ashish Vijay, Rajasthan (IN); Stephen Potter, Nuneaton (GB); Rajeeva Krishna, Bangalore (IN); and Anitha Thangavel, Karnataka (IN)
Assigned to HAMILTON SUNDSTRAND CORPORATION, Charlotte, NC (US)
Filed by Hamilton Sundstrand Corporation, Charlotte, NC (US)
Filed on Oct. 23, 2023, as Appl. No. 18/492,222.
Claims priority of application No. 202311027148 (IN), filed on Apr. 12, 2023.
Prior Publication US 2024/0345984 A1, Oct. 17, 2024
Int. Cl. G06F 13/42 (2006.01); G06F 13/362 (2006.01); G06F 13/38 (2006.01)
CPC G06F 13/4243 (2013.01) [G06F 13/362 (2013.01); G06F 13/382 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A bus controller-based page memory programmable logic device (PLD) architecture comprising:
a plurality of PLD modules, each PLD module including a PLD memory unit configured to store first data, the plurality of PLD modules including a bus controller in signal communication with the plurality of PLD modules via a universal bus interface, the bus controller comprising:
a controller input interface including a plurality of inputs configured to establish a multiplex connection between the bus controller and each of the PLD modules;
bus memory unit configured to store second data; and
a bus controller engine configured to sequentially execute a set of bus controller instructions, the bus controller engine including input multiplexing (MUX) logic to select data from the plurality of input to control data flow over the multiplex connection,
wherein one or both of the first data and the second data is transferred between the bus controller and a target PLD module among the plurality of PLD modules in response to sequentially executing the set of bus controller instructions.