US 12,487,958 B2
PCIE device positioning method and apparatus, and related device
Yongbo Sun, Jiangsu (CN); Kaizhi Lin, Jiangsu (CN); Daotong Li, Jiangsu (CN); and Binghui Zhang, Jiangsu (CN)
Assigned to SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
Appl. No. 18/572,142
Filed by SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD., Jiangsu (CN)
PCT Filed Jun. 19, 2022, PCT No. PCT/CN2022/099649
§ 371(c)(1), (2) Date Dec. 19, 2023,
PCT Pub. No. WO2023/137963, PCT Pub. Date Jul. 27, 2023.
Claims priority of application No. 202210051743.6 (CN), filed on Jan. 18, 2022.
Prior Publication US 2024/0289294 A1, Aug. 29, 2024
Int. Cl. G06F 13/14 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A Peripheral Component Interconnect Express (PCIE) device positioning method, comprising:
acquiring device information of a target PCIE device, and determining a physical slot number and PCIE bridge information of the target PCIE device according to the device information;
generating first position matching information according to the physical slot number and the PCIE bridge information;
determining, according to a first mapping relationship, position information corresponding to the first position matching information, wherein the first mapping relationship comprises a mapping relationship between the first position matching information of each PCIE device and the position information of each PCIE device; and
determining, according to the position information, a position where the target PCIE device is located;
wherein the device information comprises a Bus number, a Device number, and a Function Number; and determining the physical slot number and the PCIE bridge information of the target PCIE device according to the device information comprises:
determining, according to a second mapping relationship, the physical slot number corresponding to the Bus number, the Device number, and the Function Number, wherein the second mapping relationship comprises a mapping relationship between the Bus number, Device number and Function Number of each PCIE device, and the physical slot number of each PCIE device; and
performing PCIE bridge source tracing according to the Bus number by using a PCIE specification algorithm, so as to obtain the PCIE bridge information.