US 12,487,948 B2
Memory die interconnections to physical layer interfaces
Yang Lu, Boise, ID (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 14, 2023, as Appl. No. 18/540,427.
Claims priority of provisional application 63/476,057, filed on Dec. 19, 2022.
Prior Publication US 2024/0202145 A1, Jun. 20, 2024
Int. Cl. G06F 13/16 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1684 (2013.01) [G06F 13/1689 (2013.01); G06F 13/4234 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least two physical interfaces (PHYs) comprising a first PHY and a second PHY, each of the at least two PHYs comprising:
a chip select (CS) bus;
a command-and-address (CA) bus; and
at least one data input/output (DQ) bus; and
at least one memory die operably coupled to:
the first PHY via the CA bus of the first PHY and the at least one DQ bus of the first PHY; and
the second PHY via the CS bus of the second PHY.