US 12,487,946 B2
Connection device between DMA and DRAM using re-order buffer and interleaving and method of using the same
Seunghak Han, Seongnam-si (KR)
Assigned to Mobilint, Inc., Seoul (KR)
Filed by Mobilint, Inc., Seoul (KR)
Filed on Jul. 29, 2024, as Appl. No. 18/787,649.
Application 18/787,649 is a continuation of application No. PCT/KR2022/021349, filed on Dec. 27, 2022.
Claims priority of application No. 10-2022-0172463 (KR), filed on Dec. 12, 2022.
Prior Publication US 2024/0385973 A1, Nov. 21, 2024
Int. Cl. G06F 13/16 (2006.01); G06F 15/78 (2006.01); G06N 3/02 (2006.01)
CPC G06F 13/16 (2013.01) [G06F 15/78 (2013.01); G06N 3/02 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A connection device between a Direct Memory Access (DMA) and a Dynamic Random Access Memory (DRAM) comprising:
a slave interface connected to the DMA of a Neural Processing Unit (NPU);
a master interface connected to the DRAM having a plurality of slave ports; and
a switch configured to connect the slave interface to the master interface, and
wherein the connection device receives a data read request from the DMA of the NPU and transfers the received data read request to the DRAM, receives data or a response corresponding to the received data read request from the plurality of slave ports, and rearranges the data or the response based on an order of the received data read request so as to be transferred to the DMA of the NPU,
wherein the switch includes a scheduler configured to read instruction data required for scheduling from a first port among the plurality of slave ports, and
wherein the scheduler identifies operating conditions of a multi-core of the NPU through the instruction data, and reproduces and distributes input values, weights, convolutions, depthwise convolutions, and instruction data corresponding to the multi-core in a buffer.