US 12,487,940 B2
Configurable logic block networks and managing coherent memory in the same
Jeremy Chritz, Seattle, WA (US); and David Hulton, Seattle, WA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 20, 2022, as Appl. No. 17/664,348.
Application 17/664,348 is a continuation of application No. 17/068,370, filed on Oct. 12, 2020, granted, now 11,341,057.
Application 17/068,370 is a continuation of application No. 16/049,269, filed on Jul. 30, 2018, granted, now 10,942,861, issued on Mar. 9, 2021.
Prior Publication US 2022/0276967 A1, Sep. 1, 2022
Int. Cl. G06F 12/10 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/657 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first logic circuit comprising an algorithmic logic unit (ALU) and an input/output (I/O) interface coupled to the ALU, the first logic circuit configured to:
determine, based on a command associated with the first logic circuit, a first function and a second function different from the first function, wherein the first function and the second function are associated with operations performed using data retrieved from a memory associated with the first logic circuit;
implement, by the ALU, the first function using the data to generate a result; and
transmit an instruction at least partially based on the command to a second logic circuit via the I/O interface, wherein the instruction is configured to cause the second logic circuit to implement the second function using the result;
a control logic containing an instruction set and configured to generate the command associated with the first logic circuit, wherein the command includes an operation type portion indicating an operation type, a module number portion indicating a processing element to perform an operation, a memory address portion indicating a memory address for the data, and a tag portion;
an advanced extensible interface (AXI) configured to receive, from the ALU, an output data stream associated with implementation of the first function using the data to generate the result and convert the output data stream to AXI transactions; and
a memory mapping unit configured to align out-of-order packets based on the tag portion of the command and configured to receive the AXI transactions and identify the memory from a plurality of memories based at least in part on the AXI transactions.