US 12,487,939 B1
Virtually-indexed cache coherency using physical address proxies
John G. Favor, San Francisco, CA (US); Srivatsan Srinivasan, Cedar Park, TX (US); and Robert Haskell Utley, Austin, TX (US)
Assigned to Ventana Micro Systems Inc., Cupertino, CA (US)
Filed by Ventana Micro Systems Inc., Cupertino, CA (US)
Filed on Sep. 16, 2024, as Appl. No. 18/886,862.
Application 18/886,862 is a continuation of application No. 17/752,010, filed on May 24, 2022, granted, now 12,099,448.
Application 17/752,010 is a continuation in part of application No. 17/747,513, filed on May 18, 2022, granted, now 12,093,179.
Application 17/752,010 is a continuation in part of application No. 17/747,556, filed on May 18, 2022, granted, now 12,086,063, issued on Sep. 10, 2024.
Application 17/747,513 is a continuation in part of application No. 17/370,009, filed on Jul. 8, 2021, granted, now 11,481,332, issued on Oct. 25, 2022.
Application 17/747,513 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686, issued on Jul. 26, 2022.
Application 17/747,556 is a continuation in part of application No. 17/351,946, filed on Jun. 18, 2021, granted, now 11,397,686, issued on Jul. 26, 2022.
Application 17/747,556 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406, issued on Aug. 16, 2022.
Application 17/747,513 is a continuation in part of application No. 17/351,927, filed on Jun. 18, 2021, granted, now 11,416,406, issued on Aug. 16, 2022.
Application 17/351,927 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400, issued on Aug. 16, 2022.
Application 17/747,556 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400, issued on Aug. 16, 2022.
Application 17/351,946 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400, issued on Aug. 16, 2022.
Application 17/747,513 is a continuation in part of application No. 17/315,262, filed on May 7, 2021, granted, now 11,416,400, issued on Aug. 16, 2022.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0811 (2016.01); G06F 12/0864 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0864 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A cache memory subsystem, comprising:
a virtually-indexed virtually-tagged first-level cache;
a physically-indexed physically-tagged second-level cache, wherein each entry in the second-level cache is uniquely identified by a physical address proxy (PAP) comprising a set index and a way number of the second-level cache;
wherein the cache memory subsystem has an inclusive allocation policy such that:
each line of memory allocated into the first-level cache is also allocated into the second-level cache; and
when the second-level cache evicts a line of memory, the first-level cache also evicts the line of memory; and
wherein each entry allocated into the first-level cache stores at least a diminutive PAP (dPAP) comprising a way number and translated bits of a corresponding PAP that uniquely identifies a corresponding entry allocated into the second-level cache.