US 12,487,928 B2
Two-stage cache partitioning
Philip Abraham, Beaverton, OR (US); Stephen Van Doren, Portland, OR (US); Ritu Gupta, Cuppertino, CA (US); and Andrew Herdrich, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,471.
Prior Publication US 2023/0315632 A1, Oct. 5, 2023
Int. Cl. G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/0846 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/084 (2013.01); G06F 12/0846 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A processor comprising:
a first one or more registers to provide first information which describes a set-wise partitioning of a cache;
a second one or more registers to provide second information which describes a way-wise partitioning of the cache; and
first circuitry coupled to the first one or more registers and the second one or more registers, the first circuitry to:
receive a memory access request comprising a first address; and
identify a cache line of the cache based on the first address, the set-wise
partitioning, and the way-wise partitioning;
wherein:
the first one or more registers comprise a first plurality of registers which correspond to different ones of multiple set-wise partitions, respectively;
the cache comprises multiple segments which each comprise a same total number of sets; and
for each of the first plurality of registers, the register is to provide a respective first set of bits which is to identify one or more of the multiple segments as belonging to the corresponding set-wise partition.