US 12,487,927 B2
Remote cache invalidation
Brett S. Feero, Lake Oswego, OR (US); Dennis R. Bradford, Portland, OR (US); Gaurav Garg, San Jose, CA (US); Jeff Gonion, Campbell, CA (US); Bernard J. Semeria, Palo Alto, CA (US); James Vash, San Ramon, CA (US); and Richard F. Russo, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 20, 2024, as Appl. No. 18/582,305.
Claims priority of provisional application 63/585,020, filed on Sep. 25, 2023.
Prior Publication US 2025/0103492 A1, Mar. 27, 2025
Int. Cl. G06F 12/0808 (2016.01); G06F 12/0882 (2016.01); G06F 12/1045 (2016.01)
CPC G06F 12/0808 (2013.01) [G06F 12/0882 (2013.01); G06F 12/1045 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
coprocessor circuitry that includes:
coprocessor cache circuitry; and
cache invalidation control circuitry;
primary processor circuitry that includes:
an execution pipeline; and
primary processor cache circuitry;
wherein:
the primary processor circuitry is configured to:
map memory pages for the coprocessor circuitry;
unmap a page that was mapped for the coprocessor circuitry; and
based on the unmap and execution of a remote invalidate instruction by the execution pipeline, send a cache invalidate command to the coprocessor circuitry; and
the cache invalidation control circuitry is configured to, in response to the cache invalidate command, invalidate one or more cache lines in the coprocessor cache circuitry, where the cache invalidation control circuitry is configured to perform the invalidation without executing any instructions on the coprocessor circuitry.