| CPC G06F 12/0246 (2013.01) [G06F 11/0772 (2013.01); G06F 12/1009 (2013.01); G06F 2212/7211 (2013.01)] | 27 Claims |
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1. A memory device, comprising:
one or more memory circuits each organized as a plurality of physical memory pages, each physical memory page being associated with a physical page address, wherein each memory circuit, upon receiving a device read command or a device write command that specifies any of the physical page addresses, initiates a corresponding read or write operation on the physical memory page associated with the specified physical page address; and
a control circuit which comprises:
an external interface that receives from an external processor host read requests or host write requests, each host read request or each host write request specifying a host memory address;
an address mapping circuit configured to map each host memory address to a device memory page address in a device address space, each device memory page address being associated with a device memory page, the device memory page representing data to be stored or that is stored in one of the physical memory pages;
an ingress circuit which creates a device read command or a device write command based on each host read request or each host write request received over the external interface;
a migration circuit which creates migration read commands and migration write commands; and
a memory interface circuit, comprising:
an address translation circuit which maps each device memory page address to a corresponding physical page address; and
a command control circuit, which controls operations in the memory circuits for each read command, each write command, each migration read command, and each migration write command, providing to the memory circuits corresponding physical memory page addresses mapped by the address translation circuit,
wherein the migration circuit generates, using an address adjustment circuit, a modified device memory page address for each device memory page address, each modified device memory page address corresponding to a physical page address associated with the device memory page address; and upon occurrence of a triggering event, the migration circuit:
(a) creates a migration read command to retrieve from one of the memory circuits data stored in a first physical memory page having a first physical page address associated with a first modified device memory page address;
(b) creates a migration write command to write into one of the memory circuits the data retrieved by the migration read command into a second physical memory page having a second physical page address; and
(c) revises the address mapping in the address translation circuit to map the second physical page address to the first modified device memory page address, upon successful performance of the migration write command; and
wherein the device memory page address comprises a plurality of fields and the address adjustment circuit generates the modified device memory page address by applying a hash function on one or more fields of the device memory page address.
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