US 12,487,905 B1
User interface for formal verification of computer instructions for compatibility with a compiler architecture
Breno Rodrigues Guimaraes, Belo Horizonte (BR); Habeeb Farah, San Jose, CA (US); Andreas Tiemeyer, San Jose, CA (US); and Vaibhav Mittal, Whitefield (IN)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Dec. 12, 2022, as Appl. No. 18/079,775.
Int. Cl. G06F 11/3604 (2025.01); G06F 8/33 (2018.01); G06F 8/41 (2018.01)
CPC G06F 11/3608 (2013.01) [G06F 8/33 (2013.01); G06F 8/41 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system for formal verification of computer instructions, the system comprising:
a processor and memory coupled with a user interface, the processor configured to:
present, at the user interface, a first model that includes a data structure as generated by a compiler based on one or more instructions compatible with the compiler;
obtain, via the user interface and during a first traversal of the data structure, a first indication to modify an unmodified parameter of an instruction among the one or more instructions to a predetermined value; and
present, at the user interface in response to the indication to modify the unmodified parameter as generated by the compiler, a second indication of execution of the one or more of the instructions in an order according to a second model that corresponds to the data structure as generated by the compiler and based on a modified parameter.