| CPC G06F 9/526 (2013.01) [G06F 9/5055 (2013.01)] | 20 Claims |
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1. A processor comprising:
execution logic comprising one or more execution units for running software;
a hardware pipeline comprising fixed-function hardware;
a register bank to which the software can write descriptors specifying tasks to be processed by the hardware pipeline, wherein the register bank can hold a plurality of said descriptors at once including at least a respective descriptor of a first task and a respective descriptor of a second task;
a blocking circuit disposed between an upstream section and a downstream section of the hardware pipeline; and
control circuitry configured to trigger the upstream section to process an upstream phase of the first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed by the downstream section in a downstream phase of the first task;
wherein the control circuitry is further configured to, in response to detecting that the upstream section has finished processing the upstream phase of the first task, trigger the upstream section to start processing a upstream phase of the second task while the downstream section is still processing the downstream phase of the first task, and switch the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing from the upstream to the downstream section.
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