| CPC G06F 9/30123 (2013.01) [G06F 9/52 (2013.01)] | 20 Claims |
|
1. A processing device comprising processing circuitry, comprising:
a plurality of processors;
a memory operably coupled to the plurality of processors; and
a configuration line connecting the plurality of processors in series,
wherein each processor of the plurality of processors comprises a configuration register storing a configuration indication and a lock status register storing a lock status,
wherein the processing circuitry is configured to cause:
providing, to the configuration line, a plurality of configuration indication set signals to set configuration indications in configuration registers of the plurality of processors, and
wherein a respective one processor of the plurality of processors is configured to cause:
in response to receiving the configuration indication set signal, setting a configuration indication of the configuration indication set signal in the configuration register of the respective one processor if the lock status in the lock status register of the respective one processor is an unlocked state; and
in response to receiving the configuration indication set signal, passing the configuration indication set signal to a next processor of the respective one processor if the lock status in the lock status register of the respective one processor is a locked state,
wherein, after setting the configuration indication of the configuration indication set signal in the configuration register of the respective one processor if the lock status in the lock status register of the respective one processor is the unlocked state, the configuration indication set signal is not passed to the next processor of the respective one processor.
|