| CPC G06F 9/30101 (2013.01) [G06F 9/30123 (2013.01)] | 20 Claims |
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1. A processing apparatus comprising a processor, wherein:
the processor comprises a plurality of deferred-push processor registers;
the processor comprises processor-register control circuitry;
the processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register;
the processor-register control circuitry is configured to detect a write of a new value to a register of the deferred-push registers;
the processor-register control circuitry is configured, in response to said detection, to determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register; and
the processor-register control circuitry is configured, when the status register is determined to have the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.
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