US 12,487,802 B2
Configuration file generation for fracturable data path in a coarse-grained reconfigurable processor
Raghu Prabhakar, San Jose, CA (US); David Brian Jackson, Dana Point, CA (US); and Scott Burson, Palo Alto, CA (US)
Assigned to SambaNova Systems, Inc., Palo Alto, CA (US)
Filed by SambaNova Systems, Inc., Palo Alto, CA (US)
Filed on Feb. 21, 2024, as Appl. No. 18/583,845.
Application 18/583,845 is a continuation of application No. 18/099,214, filed on Jan. 19, 2023, granted, now 11,928,445.
Claims priority of provisional application 63/301,465, filed on Jan. 20, 2022.
Prior Publication US 2024/0192935 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 8/41 (2018.01); G06F 9/30 (2018.01); G06F 9/445 (2018.01); G06F 15/80 (2006.01)
CPC G06F 8/441 (2013.01) [G06F 9/3001 (2013.01); G06F 9/44505 (2013.01); G06F 15/80 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory machine-readable medium comprising computer instructions that, in
response to being executed by a processor, cause the processor to produce a configuration file to configure a fracturable data path of a configurable unit in an array of configurable units of a coarse-grained reconfigurable processor to generate a plurality of independent address sequences including a first address sequence generated using a first address calculation and a second address sequence generated using a second address calculation, the fracturable data path comprising a plurality of pipelined computation stages, the configuration file produced by:
analyzing the first address calculation and the second address calculation to determine to use N pipeline stages for the first address calculation and M pipeline stages for the second address calculation, wherein N and M are positive integers;
generating first configuration data for a first set of stages to produce the first address sequence and second configuration data for a second set of stages to generate the second address sequence, the first set of stages consisting of N computational stages of the plurality of pipelined computation stages and the second set of stages consisting of M computational stages of the plurality of pipelined computation stages; and
including the first configuration data and the second configuration data in the configuration file.