US 12,487,779 B2
Memory device operations for unaligned write operations
Scheheresade Virani, Frisco, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 3, 2024, as Appl. No. 18/731,756.
Application 18/731,756 is a continuation of application No. 17/822,895, filed on Aug. 29, 2022, granted, now 12,001,717.
Prior Publication US 2024/0319922 A1, Sep. 26, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory; and
one or more components configured to:
determine, based on a mapping of logical addresses to physical addresses associated with the memory, a first physical address associated with a first logical address of first data indicated by a write command,
wherein the first logical address is associated with a second size that is less than a first size associated with the logical addresses and the physical addresses, and
wherein the first physical address is associated with the first size;
read second data from a set of physical addresses corresponding to the first physical address, wherein each of the set of physical addresses is associated with the second size;
store the first data in at least one buffer of a set of buffers;
merge the second data into the set of buffers; and
cause the first data and the second data stored in the set of buffers to be written to the memory.