| CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |

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1. A flash memory controller, to be coupled between a host device and a flash memory module, comprising:
a specific buffer, for receiving and buffering specific data from the host device, the specific data to be stored into the flash memory module to form a super block, the super block being composed of a plurality of finger-shaped sub-blocks in a vertical direction and a plurality of wordlines in a horizontal direction; and
an error correction code circuit, coupled to the specific buffer, comprising:
a wordline-dimensional check code buffer, including a plurality of groups of wordline-dimensional sub-buffers, each group of wordline-dimensional sub-buffers including a plurality of sub-buffers; and
a finger-dimensional check code buffer, including a plurality of finger-dimensional sub-buffers;
wherein the error correction code circuit uses the wordline-dimensional check code buffer to perform a wordline-dimensional error correction code operation upon the specific data to generate wordline-dimensional check code data and uses the finger-dimensional check code buffer to perform a finger-dimensional error correction code operation upon an operation result of the wordline-dimensional error correction code operation with the specific data to generate finger-dimensional check code data; when a data error occurs in the super block, the wordline-dimensional check code data and the finger-dimensional check code data are used to correct the data error occurring in the super block to obtain the specific data.
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