US 12,487,745 B2
Suspending operations of a memory system
David Aaron Palmer, Boise, ID (US); Giuseppe Cariello, Boise, ID (US); and Fulvio Rori, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 10, 2024, as Appl. No. 18/830,454.
Application 18/830,454 is a continuation of application No. 17/884,429, filed on Aug. 9, 2022, granted, now 12,105,959.
Prior Publication US 2025/0077077 A1, Mar. 6, 2025
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A host system, comprising:
processing circuitry, wherein the processing circuitry is configured to cause the host system to:
transmit, to a memory system, a write command comprising first data associated with a write operation;
transmit a suspend command to suspend performance of the write operation in accordance with a read operation associated with a higher priority than the write operation;
receive, from the memory system in response to the suspend command, information associated with the write operation;
receive, from the memory system, second data associated with the read operation; and
transmit, to the memory system, the information associated with the write operation in response to receiving the second data associated with the read operation.