US 12,487,630 B2
Clock distribution network, and semiconductor apparatus and semiconductor system using the clock distribution network
Ji Hyo Kang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 8, 2024, as Appl. No. 18/406,858.
Claims priority of application No. 10-2023-0102882 (KR), filed on Aug. 7, 2023.
Prior Publication US 2025/0053190 A1, Feb. 13, 2025
Int. Cl. G06F 1/10 (2006.01); G11C 7/22 (2006.01); H03K 3/037 (2006.01); H03K 19/0185 (2006.01)
CPC G06F 1/10 (2013.01) [H03K 3/037 (2013.01); H03K 19/018521 (2013.01); G11C 7/222 (2013.01)] 26 Claims
OG exemplary drawing
 
3. A semiconductor apparatus comprising:
a global input control circuit configured to receive a system clock signal and a global enable signal to output the system clock signal as a control system clock signal when the global enable signal is enabled, to fix a logic level of the control system clock signal when the global enable signal is disabled, and to change a direct current (DC) level of the control system clock signal whenever the global enable signal is disabled; and
a global clock tree configured to receive the control system clock signal to generate a first global clock signal by buffering the control system clock signal.