US 12,487,629 B2
Clock doubler with correction for output clock cycle and clock duty cycle
Xuesong Jiang, Princeton, NJ (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Sep. 27, 2023, as Appl. No. 18/475,875.
Claims priority of provisional application 63/412,915, filed on Oct. 4, 2022.
Prior Publication US 2024/0111326 A1, Apr. 4, 2024
Int. Cl. G06F 1/08 (2006.01); G06F 1/14 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock doubler, comprising:
a calibration circuit including a ring oscillator and a first counter, wherein
the ring oscillator is configured to identify timing information for clock measurement associated with an output clock frequency; and
the first counter is configured to output the timing information for calibration of a clock providing an input clock frequency;
a delay circuit including a replica ring oscillator and a second counter, wherein
the replica ring oscillator is configured to determine a delay value for correction of the input clock frequency based on a defined delay value, wherein the replica ring oscillator is configured to determine the delay value based on a counter value corresponding to a defined value; and
the second counter is configured to output the delay value for correction of the output clock frequency having a clock frequency that is a multiple of the input clock frequency.