US 12,487,627 B1
Configurable system counter based on a hardware clock frequency
Itamar Bonne, Maccabim (IL); Ofer Naaman, Hod Hasharon (IL); Benny Pollak, Yad Binyamin (IL); and Max Chvalevsky, Mevaseret Zion (IL)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Sep. 28, 2023, as Appl. No. 18/374,597.
Int. Cl. G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) 21 Claims
OG exemplary drawing
 
1. A system comprising:
a hardware component;
a component clock; and
a computing device comprising data processing hardware and memory hardware, the computing device configured to:
determine a component clock frequency indicative of a frequency of clock processes of the component clock, wherein a first count of the clock processes of the component clock is indicative of a first plurality of clock cycles, wherein the first count is utilized by the hardware component to perform one or more functions;
obtain an input indicative of a desired system clock frequency, wherein the component clock frequency and the desired system clock frequency have different frequency values;
determine a difference between the component clock frequency and the desired system clock frequency;
determine a second count indicative of a second plurality of clock cycles based on the difference between the component clock frequency and the desired system clock frequency, wherein to determine the second count, the computing device is further configured to, for each clock cycle of the first plurality of clock cycles:
determine a remainder based on the component clock frequency and the desired system clock frequency, and
generate a value of the second count for the clock cycle based on the remainder;
identify one or more events associated with the system; and
timestamp the one or more events according to the second count.