| CPC G05F 1/575 (2013.01) [G05F 1/565 (2013.01); G05F 1/59 (2013.01); G05F 3/24 (2013.01)] | 15 Claims |
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1. An electronic device, comprising:
an input voltage node and a load node;
a first integrated circuit including:
a first power transistor connected between the input voltage node and the load node; and
a first regulation circuit configured to generate first and second sense currents which are representative of an output current of the first power transistor; and
a second integrated circuit including:
a second power transistor connected between the input voltage node and the load node; and
a second regulation circuit configured to generate third and fourth sense currents which are representative of an output current of the second power transistor;
a first resistor external to the first and second integrated circuits and coupled to receive the first sense current such that a first voltage formed across the first resistor is representative of the output current of the first power transistor;
a second resistor external to the first and second integrated circuits and coupled to receive the third sense current such that a second voltage formed across the second resistor is representative of the output current of the second power transistor; and
a third resistor external to the first and second integrated circuits and coupled to receive the second and fourth sense currents such that a third voltage formed across the third resistor is representative of an average of the output currents of the first and second power transistors;
wherein the first regulation circuit comprises:
a first amplifier having inputs coupled to receive the first and third voltages, the first amplifier configured to source current to its output when the first voltage is greater than the third voltage but to sink current from its output when the first voltage is less than the third voltage; and
a second amplifier having inputs coupled to receive a soft start voltage and a voltage generated at the output of the first amplifier, wherein an output of the second amplifier is coupled to drive a control terminal of the first power transistor;
wherein the first regulation circuit is configured to cause the first power transistor to decrease its output current when the first sense current is greater than an average of the second and fourth sense currents;
wherein the first regulation circuit is configured to cause the first power transistor to increase its output current when the first sense current is less than an average of the second and fourth sense currents; and
wherein the second regulation circuit comprises:
a third amplifier having inputs coupled to receive the second and third voltages, the third amplifier configured to source current to its output when the second voltage is greater than the third voltage but to sink current from its output when the second voltage is less than the third voltage; and
a fourth amplifier having inputs coupled to receive a soft start voltage and a voltage generated at the output of the third amplifier, wherein an output of the fourth amplifier is coupled to drive a control terminal of the second power transistor;
wherein the second regulation circuit is configured to cause the second power transistor to decrease its output current when the third sense current is greater than an average of the second and fourth sense currents; and
wherein the second regulation circuit is configured to cause the second power transistor to increase its output current when the third sense current is less than an average of the second and fourth sense currents.
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