US 12,487,282 B2
On-chip distribution of test data for multiple dies
Arie Margulis, Markham (CA); Tassanee Payakapan, Markham (CA); and Yuan Chao, Beijing (CN)
Assigned to Advanced Micro Devices Products (China) Co., Ltd., Beijing (CN); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed by Advanced Micro Devices Products (China) Co. Ltd., Beijing (CN); and ATI TECHNOLOGIES ULC, Markham (CA)
Filed on Dec. 28, 2021, as Appl. No. 17/564,129.
Prior Publication US 2023/0204662 A1, Jun. 29, 2023
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31713 (2013.01); G01R 31/31723 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of semiconductor dies comprising multiple die types of semiconductor dies;
a set of pins configured to receive test input data from a device external to the integrated circuit; and
a test distribution circuitry configured to concurrently distribute the received test input data to a first subset of the plurality of semiconductor dies belonging to a first die type of the multiple die types of semiconductor dies based on received control information.