US 12,487,254 B2
Packaged current sensor integrated circuit
Shixi Louis Liu, Hooksett, NH (US)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Mar. 13, 2023, as Appl. No. 18/182,434.
Application 18/182,434 is a continuation in part of application No. 18/053,480, filed on Nov. 8, 2022, granted, now 12,163,983.
Application 18/053,480 is a continuation in part of application No. 17/654,254, filed on Mar. 10, 2022, granted, now 11,768,229.
Application 17/654,254 is a continuation in part of application No. 17/409,011, filed on Aug. 23, 2021, granted, now 11,519,946, issued on Dec. 6, 2022.
Prior Publication US 2023/0221355 A1, Jul. 13, 2023
Int. Cl. G01R 15/20 (2006.01); G01R 19/00 (2006.01); G01R 33/07 (2006.01); H01L 23/495 (2006.01)
CPC G01R 15/202 (2013.01) [H01L 23/49575 (2013.01); G01R 15/207 (2013.01); G01R 19/0092 (2013.01); G01R 33/072 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A current sensor integrated circuit package comprising:
a primary conductor having an input portion into which a current flows, an output portion from which the current flows, and an exposed portion, wherein the input portion has a reduced area edge and the output portion has a reduced area edge;
a secondary lead having an exposed portion spaced from the exposed portion of the primary conductor by an isolation distance of at least 2.0 mm, wherein an elongated portion of the secondary lead is offset with respect to the exposed portion of the secondary lead;
a semiconductor die disposed adjacent to the primary conductor and positioned on an insulator portion;
at least one magnetic field sensing element supported by the semiconductor die, wherein the at least one magnetic field sensing element is configured to generate a signal corresponding to the current that flows in the primary conductor; and
a package body enclosing the semiconductor die and a portion of the primary conductor and comprising a first cutout in a first side edge configured to expose the reduced area edge of the input portion of the primary conductor and a second cutout on a second side edge configured to expose the reduced area edge of the output portion of the primary conductor, wherein the first side edge of the package body is substantially parallel with respect to the second side edge of the package body.