| CPC H10B 43/50 (2023.02) [H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |
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1. A method of manufacturing a semiconductor device, comprising:
preparing a substrate comprising a cell array region and a word line contact region;
forming a stack of alternating first and second layers on the substrate, each of the second layers extending in a first direction less than a previous one of the second layers to define a landing portion of the previous one of the second layers in the word line contact region;
forming a first hole through at least one of a plurality of the first layers and at least one of a plurality of the second layers in the stack such that the first hole penetrates one of the landing portions;
etching the plurality of the first layers to widen portions of the first hole at least under [ respective ones of ] the plurality of the second layers;
forming a support insulating layer within the first hole including the widened portions;
exposing part of the landing portions [ by removing a bottom portion of the support insulating layer] ; and
forming contact plugs such that each of the contact plugs [ is ] in contact with a respective one of the landing portions.
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