	US RE50,222 E1
	Non-planar gate all-around device and method of fabrication thereof
Willy Rachmady, Beaverton, OR (US); Ravi Pillarisetty, Portland, OR (US); Van H. Le, Portland, OR (US); Jack T. Kavaileros, Portland, OR (US); Robert S. Chau, Beaverton, OR (US); and Jessica S. Kachian, Portland, OR (US)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Aug. 24, 2021, as Appl. No. 17/410,406.
Application 17/410,406 is a continuation of application No. 14/582,131, filed on Dec. 23, 2014, granted, now 9,252,275, issued on Feb. 2, 2016.
Application 14/582,131 is a continuation of application No. 13/997,118, granted, now 8,987,794, issued on Mar. 24, 2015, previously published as PCT/US2011/067234, filed on Dec. 23, 2011.
Application 17/410,406 is a reissue of application No. 14/946,744, filed on Nov. 19, 2015, granted, now 10,418,487, issued on Sep. 17, 2019.
Int. Cl. H01L 29/78 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/7848 (2013.01) [H01L 29/045 (2013.01); H01L 29/0669 (2013.01); H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/165 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 2029/7858 (2013.01)]

15 Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a first material, the first material having a first lattice constant;

a source region above the substrate the source region comprising a second material, the second material having a second lattice constant different than the first lattice constant;

a drain region above the substrate, the drain region comprising the second material;

a nanowire, the nanowire being coupled to the source region and being coupled to the drain region, the nanowire comprising a third material, the third material having a third lattice constant substantially the same as the second lattice constant, wherein the source region and the drain region provide a uniaxial stress to the nanowire;

a gate dielectric layer around at least a portion of the nanowire, wherein the gate dielectric layer is directly on the third material of the nanowire; and

a gate electrode around at least a portion of the nanowire and, the gate electrode being separated from the nanowire by at least the gate dielectric layer [ ,

wherein the second material is the same as the third material] .