| CPC H10B 63/845 (2023.02) [H10B 63/34 (2023.02)] | 9 Claims |
|
1. A memory device comprising:
a first conductor, a second conductor, a third conductor, and a fourth conductor;
a first insulator, a second insulator, and a third insulator;
a first semiconductor and a second semiconductor; and
a first transistor,
wherein the first conductor extends in a first direction,
wherein, on a side surface extending in the first direction of the first conductor, the first insulator is adjacent to the first conductor, the first semiconductor is adjacent to the first insulator, the second insulator is adjacent to the first semiconductor, the second semiconductor is adjacent to the second insulator, and the third insulator is adjacent to the second semiconductor,
wherein the memory device comprises a first region and a second region,
wherein in the first region, the second conductor is adjacent to the third insulator,
wherein in the second region, the third conductor is adjacent to the third insulator,
wherein, in the second region, the fourth conductor is between the second insulator and the second semiconductor, and
wherein the first semiconductor and the second semiconductor are electrically connected to one of a source and a drain of the first transistor.
|