CPC H10B 41/27 (2023.02) [G11C 5/06 (2013.01); H01L 23/5386 (2013.01); H10B 43/27 (2023.02)] | 20 Claims |
1. A three-dimensional (3D) semiconductor memory device, comprising:
stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures comprises interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate;
conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and
a protective structure covering a top surface of the semiconductor substrate between the stack structures,
wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers,
wherein the protective structure covers a sidewall of the lowermost interlayer insulating layer.
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