US 12,156,401 B2
Three-dimensional semiconductor memory device and a method of manufacturing the same
Joongchan Shin, Seoul (KR); Byeungmoo Kang, Hwaseong-si (KR); and Sangyeon Han, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 17, 2021, as Appl. No. 17/477,634.
Claims priority of application No. 10-2020-0120674 (KR), filed on Sep. 18, 2020.
Prior Publication US 2022/0093626 A1, Mar. 24, 2022
Int. Cl. H10B 41/27 (2023.01); G11C 5/06 (2006.01); H01L 23/538 (2006.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 5/06 (2013.01); H01L 23/5386 (2013.01); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) semiconductor memory device, comprising:
stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures comprises interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate;
conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and
a protective structure covering a top surface of the semiconductor substrate between the stack structures,
wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers,
wherein the protective structure covers a sidewall of the lowermost interlayer insulating layer.