	US 12,156,396 B2
	Memory device, semiconductor device, and electronic device
Shuhei Nagatsuka, Atsugi (JP); Tatsuya Onuki, Atsugi (JP); Takahiko Ishizu, Sagamihara (JP); Kiyoshi Kato, Atsugi (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/424,664
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Nov. 22, 2019, PCT No. PCT/IB2019/060053 § 371(c)(1), (2) Date Jul. 21, 2021, PCT Pub. No. WO2020/157558, PCT Pub. Date Aug. 6, 2020.
Claims priority of application No. 2019-013469 (JP), filed on Jan. 29, 2019.
Prior Publication US 2022/0108985 A1, Apr. 7, 2022
Int. Cl. H10B 12/00 (2023.01); G11C 5/02 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); G11C 11/405 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01)

CPC H10B 12/00 (2023.02) [G11C 5/02 (2013.01); H01L 27/1225 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); G11C 11/405 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01)]

13 Claims

1. A memory device comprising:

a semiconductor substrate; and

first to I-th layers, where I is an integer greater than or equal to 2; and

an insulator,

wherein the semiconductor substrate comprises a peripheral circuit comprising a transistor formed in the semiconductor substrate,

wherein a k-th layer comprises a memory cell array comprising a thin film transistor formed in the k-th layer, where k is an integer greater than or equal to 1 and less than or equal to I,

wherein the first layer is stacked above the semiconductor substrate,

wherein a j-th layer is stacked above a j-1-th layer, where j is an integer greater than or equal to 2 and less than or equal to I,

wherein the insulator covers side surfaces of the first to I-th layers and a top surface of the I-th layer, and

wherein the insulator comprises silicon nitride or silicon nitride oxide.