US 12,156,328 B2
Printed circuit board with integrated fusing and arc suppression
Kaijam M. Woodley, Brown Deer, WI (US); Michael K. Balck, East Grand Rapids, MI (US); and Matthew J. Koebert, Menomonee Falls, WI (US)
Assigned to Eaton Intelligent Power Limited, Dublin (IE)
Filed by Eaton Intelligent Power Limited, Dublin (IE)
Filed on Jul. 7, 2023, as Appl. No. 18/219,460.
Application 18/219,460 is a division of application No. 16/702,723, filed on Dec. 4, 2019, granted, now 11,729,906.
Claims priority of provisional application 62/778,391, filed on Dec. 12, 2018.
Prior Publication US 2023/0354512 A1, Nov. 2, 2023
Int. Cl. H05K 1/02 (2006.01); H01H 69/02 (2006.01); H01H 85/02 (2006.01); H01H 85/046 (2006.01); H01H 85/08 (2006.01); H01H 85/10 (2006.01)
CPC H05K 1/0293 (2013.01) [H01H 69/022 (2013.01); H01H 85/0241 (2013.01); H01H 85/046 (2013.01); H01H 2085/0275 (2013.01); H01H 85/08 (2013.01); H01H 85/10 (2013.01); H05K 2201/10181 (2013.01)] 20 Claims
OG exemplary drawing
 
10. A method comprising:
etching a conductive trace substrate on an electrically insulating substrate to form a circuit trace comprising: non-linear segments arranged adjacent to one and other; and one or more fusible links in the circuit trace, each of the one or more fusible links configured to open in response to receiving an electrical overage;
encapsulating each of the one or more fusible links with a dielectric encapsulant configured to prevent open circuit arcing by reflow into a respective open fusible link; and
forming isolation gaps in the electrically insulating substrate, the isolation gaps surrounding the non-linear segments such that each non-linear segment is separated from the other non-linear segments.