an inphase-quadrature (I-Q) merged phase interpolator circuit, the I-Q merged phase interpolator circuit including an I-phase mixer and a Q-phase mixer, the I-Q merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal;

a sampler circuit configured to sample input data based on the first clock pair and the second clock pair; and

a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit,

wherein the I-Q merged phase interpolator circuit is further configured to,

share analog inputs between the I-phase mixer and the Q-phase mixer based on the control signal, the sharing the analog inputs including outputting a current as the analog inputs through at least one activated path among a plurality of paths based on the control signal.