US 12,155,384 B2
Reference clock frequency correction by mixing with digitally-controlled low-frequency compensation signal
Nikola Katic, Toronto (CA); and Javid Musayev, Toronto (CA)
Assigned to Stathera IP Holding, Inc., Montreal (CA)
Filed by Stathera IP Holdings Inc., Montreal (CA)
Filed on Apr. 13, 2023, as Appl. No. 18/300,188.
Claims priority of provisional application 63/330,542, filed on Apr. 13, 2022.
Prior Publication US 2023/0336162 A1, Oct. 19, 2023
Int. Cl. H03K 3/011 (2006.01); G06F 1/02 (2006.01); H03B 1/04 (2006.01); H03B 5/04 (2006.01); H03B 5/30 (2006.01); H03B 21/00 (2006.01); H03K 5/00 (2006.01); H03K 5/135 (2006.01); H03L 1/00 (2006.01)
CPC H03K 3/011 (2013.01) [G06F 1/022 (2013.01); H03B 1/04 (2013.01); H03B 5/04 (2013.01); H03B 5/30 (2013.01); H03B 21/00 (2013.01); H03K 5/00006 (2013.01); H03K 5/135 (2013.01); H03L 1/00 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system, comprising:
a compensation module configured to (i) receive, as input, an oscillator signal and one or more control signals, (ii) based on the oscillator signal and the one or more control signals, generate a discretized sinusoidal signal having a controllable frequency, (iii) determine a compensation signal based on the discretized sinusoidal signal, and (iv) output the compensation signal; and
a mixer block configured to (i) receive, as input, the compensation signal and the oscillator signal, and (ii) generate an output clock signal by mixing the compensation signal with the oscillator signal.