US 12,155,383 B1
Reset mechanism for an adder or a multiplier having paraelectric material
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/493,585.
Application 17/493,585 is a continuation of application No. 17/449,748, filed on Oct. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/23 (2006.01); G06F 7/575 (2006.01); H10N 30/853 (2023.01)
CPC H03K 19/23 (2013.01) [G06F 7/575 (2013.01); H10N 30/853 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises paraelectric material; and
a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the paraelectric material, wherein the reset mechanism is to reset second terminals of the set of capacitors during a reset phase separate from an evaluation phase, and wherein the logic comprises one or more NOR gates controllable by a reset control.